PLL Clock output warning message

I am routing the output of one of the PLL's (Cyclone II) to a pin E14 which is a described as a PLL output "pll2_outp".

Yet Quartus still gives me the following warning, telling me to "Use PLL dedicated clock outputs to ensure jitter performance".

warning: pll "rcclock:rcclock|rmyclock:myclock|altpll:altpll_component|pll" output port clk[2] feeds output pin "sdram_clk" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance

Does anyone know why I still get this warning in spite of the fact that I am using a dedicated PLL pin to output my PLL clock? Here are the Megafunction parameters if that helps...

defparam

altpll_component.clk0_divide_by = 1,

altpll_component.clk0_duty_cycle = 50,

altpll_component.clk0_multiply_by = 4,

altpll_component.clk0_phase_shift = "500",

altpll_component.clk2_divide_by = 1,

altpll_component.clk2_duty_cycle = 50,

altpll_component.clk2_multiply_by = 4,

altpll_component.clk2_phase_shift = "0",

altpll_component.compensate_clock = "CLK0",

altpll_component.gate_lock_counter = 1048575,

altpll_component.gate_lock_signal = "YES",

altpll_component.inclk0_input_frequency = 37593,

altpll_component.intended_device_family = "Cyclone II",

altpll_component.invalid_lock_multiplier = 5,

altpll_component.lpm_type = "altpll",

altpll_component.operation_mode = "NORMAL",

altpll_component.port_activeclock = "PORT_UNUSED",

altpll_component.port_areset = "PORT_USED",

altpll_component.port_clkbad0 = "PORT_UNUSED",

altpll_component.port_clkbad1 = "PORT_UNUSED",

altpll_component.port_clkloss = "PORT_UNUSED",

altpll_component.port_clkswitch = "PORT_UNUSED",

altpll_component.port_configupdate = "PORT_UNUSED",

altpll_component.port_fbin = "PORT_UNUSED",

altpll_component.port_inclk0 = "PORT_USED",

altpll_component.port_inclk1 = "PORT_UNUSED",

altpll_component.port_locked = "PORT_USED",

altpll_component.port_pfdena = "PORT_UNUSED",

altpll_component.port_phasecounterselect = "PORT_UNUSED",

altpll_component.port_phasedone = "PORT_UNUSED",

altpll_component.port_phasestep = "PORT_UNUSED",

altpll_component.port_phaseupdown = "PORT_UNUSED",

altpll_component.port_pllena = "PORT_UNUSED",

altpll_component.port_scanaclr = "PORT_UNUSED",

altpll_component.port_scanclk = "PORT_UNUSED",

altpll_component.port_scanclkena = "PORT_UNUSED",

altpll_component.port_scandata = "PORT_UNUSED",

altpll_component.port_scandataout = "PORT_UNUSED",

altpll_component.port_scandone = "PORT_UNUSED",

altpll_component.port_scanread = "PORT_UNUSED",

altpll_component.port_scanwrite = "PORT_UNUSED",

altpll_component.port_clk0 = "PORT_USED",

altpll_component.port_clk1 = "PORT_UNUSED",

altpll_component.port_clk2 = "PORT_USED",

altpll_component.port_clk3 = "PORT_UNUSED",

altpll_component.port_clk4 = "PORT_UNUSED",

altpll_component.port_clk5 = "PORT_UNUSED",

altpll_component.port_clkena0 = "PORT_UNUSED",

altpll_component.port_clkena1 = "PORT_UNUSED",

altpll_component.port_clkena2 = "PORT_UNUSED",

altpll_component.port_clkena3 = "PORT_UNUSED",

altpll_component.port_clkena4 = "PORT_UNUSED",

altpll_component.port_clkena5 = "PORT_UNUSED",

altpll_component.port_extclk0 = "PORT_UNUSED",

altpll_component.port_extclk1 = "PORT_UNUSED",

altpll_component.port_extclk2 = "PORT_UNUSED",

altpll_component.port_extclk3 = "PORT_UNUSED",

altpll_component.valid_lock_multiplier = 1;

endmodule