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Altera_Forum's avatar
Altera_Forum
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13 years ago

pll clock network delay

I am getting the following clock delays in timing analysis: Roughly 4 ns in routing clock from PLL to clock input of altsyncram. I am looking for suggestions on what I am doing wrong here. H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Then the clock generated by the PLL is probably already 4 ns ahead of the PLL's input clock, in order to compensate the 4 ns delay through the network.

But the 4 ns delay is always there and always shows up in the report.