Please help with this requirement about source synchronous interface

I have a FPGA generating a clock output and data output(updated at the rising edge of the same clock).

And a second FPGA is using the clock generated by the first FPGA to sample the data from the first FPGA.

The thing is I would also like to sample data with rising edge in the second FPGA. So I need to figure out a way to delay the data from the first FPGA or delay the clock from the first FPGA such that the second FPGA would not sample the data which has just changed or will very soon change...

What's the best solution for this? Someone suggested to invert the clock and feed the second FPGA with the inverted clock such that it could sample the data in the middle of the data window.

Is there a measurable way to specify the delay between output clock and output data in the first FPGA, like making the data delayed after some nanoseconds than clock before going out of the chip(Will set_output_delay do this job?).

Thanks a lot.