Are you using a dev. board? What is the frequency of the fpga clock? The timer is based on the clock period. The code looks like:
entity....
architecture arch of ent_name is
begin
process(rst, clk)
begin
if(rst='1') then
cont_reg <= ( others=>'0');
elsif(clk'event and clk='1') else
cont_reg <= cont_prox;
end if;
end process;
cont_prox <= cont_reg + 1 when ( cont_reg < timeout ) else
cont_reg;
start <= '0' when ( cont_reg < timeout ) else
'1';
end architecture arch;
The signal "start" goes up to '1' when expires the timer. you enable the circuit with this signal. The constant timeout depends of clock period.