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dnortm
New Contributor
New ContributorPlatform Designer Output Mismatch in Simulation Generator
I just created my first Qsys file with my own component and wanted to simulate this design with my own testbench file (Quartus Prime Pro 18.1). When calling "com" in msim_setup.tcl, I get an error sa...
Vicky1
Regular Contributor
Regular ContributorHi,
It was an issue with v16.1 pro but it has been fixed in v17.1,
will conform with v18.1pro.
Best Regards
Vikas Jathar
(This message was posted on behalf of Intel Corporation)
