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dnortm
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8 years ago

Platform Designer Output Mismatch in Simulation Generator

I just created my first Qsys file with my own component and wanted to simulate this design with my own testbench file (Quartus Prime Pro 18.1). When calling "com" in msim_setup.tcl, I get an error sa...
dnortm's avatar
dnortm
Icon for New Contributor rankNew Contributor
8 years ago

Small update: Found a solution to the upper problem.

In the Component Editor one of my three files was marked with the attribute "Top-level file", but the "Top-level Module" field was grey. After clicking on "Analyze HDL files" the "Top-level Module" has been updated and the files have been generated correctly! I'd still say, that this is an undefined behaviour and a bug, but there seems to be a solution for this.