Platform Designer Import AXI Master Component: Error: Data width must be of power of two and between 8 and 4096

That works. Thank you. Is it common practice to have a set of directories with a _hw.tcl and associated RTL somewhere, then to point to that from Platform Designer? I know with the IP packager tool in Xilinx, this is the preferred workflow.

Another issue I am having, and I can open another thread if need be, is that it seems like when I generate t he testbench system there is a file that is supposed to wrap the RTL in the new_component.v file from the component that the top level generated platform designer RTL file is instantiating. The module name is something like <name of the platform designer>_<name of the component>. I assume inside this module, there would be an instantiation of what is in new_component.v where I wrote my RTL

# ** Error: (vsim-3033) ./../fpga_ram_sim_tb/simulation/submodules/fpga_ram_sim.v(44): Instantiation of 'fpga_ram_sim_oc_axi_lite_bfm_0' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /fpga_ram_sim_tb/fpga_ram_sim_inst File: ./../fpga_ram_sim_tb/simulation/submodules/fpga_ram_sim.v