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MAtte's avatar
MAtte
Icon for New Contributor rankNew Contributor
7 years ago

Platform Designer fails to generate Verilog simulation model - "Error during execution of script generate_hps_sdram.tcl"

This problem recently started happening with my own project, but it can also be replicated with the DE10_Standard_GHRD project from Terasic's DE10-Standard_v.1.2.8_SystemCD. I am using Platform Desi...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Michael,

Firewall settings can interfere with the JTAG Server.

Can you please check with your admin once, We dont have any setting to tell Platform Designer to leave the firewall alone.

Regards

Anand