Platform Designer fails to generate Verilog simulation model - "Error during execution of script generate_hps_sdram.tcl"

Thanks for looking at this.

It would add up with what I have seen if the issue was to do with Quartus trying to set a firewall rule: this project used to generate OK for me too, and the start of the problem may have been when out network admin made some changes to the company network configuration.

I have checked that jtagserver.exe (same path as in the generate log) is enabled in the firewall for all network types, see below:

but I note that I have to click on the 'Change settings' button with a shield icon on it before the firewall rules are editable - perhaps this means they are locked against being changed by software.

It seems a bit odd that the simulation model generation process wants to change firewall settings (and it fails if it can't change them even when they are already set correctly) but it would explain what I am seeing.

Now the question is what I can do to get things working again. Do I need to ask my network admin to change some management setting? Is there anyway I can tell Platform Designer to leave the firewall alone?

Thanks,

Michael