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MAtte
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7 years ago

Platform Designer fails to generate Verilog simulation model - "Error during execution of script generate_hps_sdram.tcl"

This problem recently started happening with my own project, but it can also be replicated with the DE10_Standard_GHRD project from Terasic's DE10-Standard_v.1.2.8_SystemCD. I am using Platform Desi...
MAtte's avatar
MAtte
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7 years ago

Is it telling me that the error is coming from in nios2-bsp, which comes up at the end of both groups of error messages?

Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: C:/programfiles/altera/18.0/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: child process exited abnormally
Error: fpga_interfaces: 2019.02.14.15:16:55 Error: s0: C:/programfiles/altera/18.0/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: fpga_interfaces: 2019.02.14.15:16:55 Error: s0: child process exited abnormally