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AlexBeasley's avatar
AlexBeasley
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Platform designer 21.3 pro missing clock_source block

Hi there, I am using Intel Quartus Prime Pro 21.3 and I'm attempting to create a NIOS II subsystem through platform designer 21.3. The problem I have is that there is no clock_source block so I c...
  • sstrell's avatar
    sstrell
    4 years ago

    It doesn't exist in Pro. It was broken up into the clock and reset bridge IPs, which behave exactly the same. If you have a Standard design that does include the clock source component, it will still work in Pro, but you can't create a new clock source component in Pro.

AlexBeasley's avatar
AlexBeasley
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi there,

Thanks for your quick response. So, potentially silly question incoming, but if I have a NIOS II design and I'm using a clock and reset bridge, what frequency clock should be passed to the NIOS II core? (I did try with a 50MHz clock being passed through the FPGA fabric via a clock bridge into a NIOS II design, however this failed when attempting to program the NIOS)

Thanks
Alex

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Whatever clock speeds that are supported by Nios should work. I don't know them off-hand. Whether it's the clock source component or the clock bridge, it's basically just wires distributing the clock to components in the system, so it should not affect the operation of components in the system if you change the IP to the clock bridge.