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amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago
Solved

Pipeline Factor in SignalTap

Hello, In SignalTap there is an option to add the Pipeline to the signals. Should the pipeline acts as synchronizers? Will the set_false_path constraints be added automatically? Thanks!
  • FvM's avatar
    FvM
    3 years ago

    Hello,

    Debug Tools User Guide explains:

    "The Pipeline factor setting indicates the number of pipeline registers that the Intel
    Quartus Prime software can add to boost the fMAX of the Signal Tap Logic Analyzer."

    https://cdrdv2.intel.com/v1/dl/getContent/667125?fileName=ug-qps-debug-683552-667125.pdf

    Not related to synchronizers. There's no specific feature to support the consistent capture of asynchronous signals. Signaltap operation is described so:

    "Synchronous sampling of data nodes using the same clock tree driving the logic under test."

    Regards

    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,

Debug Tools User Guide explains:

"The Pipeline factor setting indicates the number of pipeline registers that the Intel
Quartus Prime software can add to boost the fMAX of the Signal Tap Logic Analyzer."

https://cdrdv2.intel.com/v1/dl/getContent/667125?fileName=ug-qps-debug-683552-667125.pdf

Not related to synchronizers. There's no specific feature to support the consistent capture of asynchronous signals. Signaltap operation is described so:

"Synchronous sampling of data nodes using the same clock tree driving the logic under test."

Regards

Frank