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AThom47's avatar
AThom47
Icon for New Contributor rankNew Contributor
5 years ago

pin placement error after upgrade from 18.0 pro to 21.2 pro

Hi, I have an Arria10 design that compiles fine in quartus 18.0 pro but throws the following error after upgrading to quartus 21.2 pro: "Error (175020): The Fitter cannot place logic pin in regio...
AnilErinch_A_Intel's avatar
AnilErinch_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Andre,

You can create a quartus.ini file and add the content to it.

Please see the below links on creation of ini file and using the same to change IP parameters.

https://www.macnica.co.jp/business/semiconductor/support/faqs/intel/130917/


https://www.intel.com/content/dam/www/programmable/us/en/kdb/fb470823/A10-PLL-Cascading-or-Non_dedicated-Clock-Path-Workaround-Guideline-for-Altera-PHYLite-IP_Rev1.pdf


Please let us know the feedback.



Thanks and Regards

Anil