pi controller i verilog

The model below is not synthesizable.

$real is not supported in synthesis.

Additionally, most of the logic is not synchronous. Perhaps the HDL compiler from MathWorks is only generating a simulation model, not a synthesizable one.

-James

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i used matlab hdl coder to design the pi controller. but when I use it an error occurs

it shows $bitstoreal is not supported

2 real value is not supported.

any help

thanku

// -------------------------------------------------------------

//

// File Name: hdlsrc\untitled\PI_Controller.v

// Created: 2018-02-27 12:02:47

//

// Generated by MATLAB 9.0 and HDL Coder 3.8

//

// -------------------------------------------------------------

// -------------------------------------------------------------

//

// Module: PI_Controller

// Source Path: untitled/PI Controller

// Hierarchy Level: 1

//

// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module PI_Controller

(

clk,

reset,

enb,

u,

y

);

input clk;

input reset;

input enb;

input [63:0] u; // double

output [63:0] y; // double

real u_double; // double

real Proportional_Gain_out1; // double

real Integral_Gain_out1; // double

real Integrator_x_reg; // double

real Integrator_u_add; // double

real Sum_out1; // double

always @* u_double = $bitstoreal(u);

always @* Proportional_Gain_out1 = 0.0349 * u_double;

always @* Integral_Gain_out1 = 2.0 * u_double;

always @* Integrator_u_add = Integrator_x_reg + Integral_Gain_out1;

always @(posedge clk or posedge reset)

begin : Integrator_reg_process

if (reset == 1'b1) begin

Integrator_x_reg <= 0.0;

end

else begin

if (enb) begin

Integrator_x_reg <= Integrator_u_add;

end

end

end

always @* Sum_out1 = Proportional_Gain_out1 + Integrator_x_reg;

assign y = $realtobits(Sum_out1);

endmodule // PI_Controller

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