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Honored Contributor
Honored Contributorperformance problems with std_logic_vector
I have a VHDL project that I build with Quartus. I developed the project with a signal std_logic_vector(0 to 15) and I have several places where I compare bits (0 to 3) with constant/literal values l...
Altera_ForumHonored Contributor
Honored ContributorIm guessing those bits are generated from different logic. Without seeing how select is generated, its impossible to tell.
Do you have any timing assignments? Have you run timequest? what do you mean by "it runs significantly slower? have you registered the outputs? is select registered? Post all the code so maybe we can get an idea.
