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Altera_Forum
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7 years ago

Peculiar Problem with Quartus 17.0 lite

I am facing a peculiar problem while synthesizing with Quartus 17.0 lite for MAX 10 FPGA. I was just trying to interface FPGA to LTC2400 ADC in free running mode. The program basically receive...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi one thing that was overlooked by me is the critical warning which says that I have not provided any sdc constraints file. Could that be the cause of the random variations. This is because now I am experiencing a opposite result with reference to post1.