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Ulrich's avatar
Ulrich
Icon for New Contributor rankNew Contributor
4 years ago
Solved

PCIE Reset

I am using a STRATIX 10 1GS040HH3F35E3VG with Quartus Prime Pro version 21.4. I locked the npor_pin_perst of pcie hip to IO pin AP26, which is labelled as ...,nPERSTL0,.. Now fitter reports an e...
  • skbeh's avatar
    skbeh
    4 years ago

    For ND0 package device that you have selected, there is an additional setting need to add in the .qsf, in order to use the crete 3VIO instead of the levelshifters.
    set_instance_assignment -name USE_AS_3V_GPIO ON -to pin_name
    Example: set_instance_assignment -name USE_AS_3V_GPIO ON -to pcie_hip_npor_pin_perst

    Refer to this KDB solution:
    Can the 3.0V I/O banks in Stratix 10 devices support I/O standards of 2.5V, 1.8V, 1.5V or 1.2V?
    https://www.intel.com/content/www/us/en/support/programmable/articles/000074575.html

skbeh's avatar
skbeh
Icon for Contributor rankContributor
4 years ago

PCIe IP Core has two, asynchronous, active low reset inputs, npor and pin_perst.
You mentioned that you connect npor_pin_perst to nPERSTL0. Is it means you connect both npor and pin_perst to nPERSTL0?

According to S10 PCIe User Guide page 47, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf
pin_perst of bottom left PCIe hard IP must be connected to nPERSTL0. While npor is connect to other IO pin.

You can also refer to some of the S10 PCIe example available at below link for their npor and pin_perst connection.
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html

If you still have problem with your design, please attach your Quartus design here.

Ulrich's avatar
Ulrich
Icon for New Contributor rankNew Contributor
4 years ago

Hello skbeh,

npo_pin_perst is just the name of the signal coming from qsys design. It is just the pin_perst, I connected. May this problem has nothing to do with PCIE, because I got an error containing "LEVELSHIFT..." also when assigning a particular signal to bank 3C, which is the only 3.3 V bank. As nPERSTL0 is located in a 3 V bank, maybe that's the same reason. Do you know what this "LEVELSHIFT" measns ?