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Markgel's avatar
Markgel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

PCIe hard IP BAR to On-chip memory addressing

using Cyclone IV hard ip and On-chip memory 32B mapped to 0x-0x1F BAR0 mapped to 0xA1200000-0xA0001F Reading BAR0 at offset 0 should have access first byte of On-chip memory? Reading 0xff instea...
  • JohnT_Altera's avatar
    JohnT_Altera
    5 years ago

    Hi,


    May I know if you enable the PCIe BAR0? Have you try to performed SignalTap?


JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.