Forum Discussion
Markgel
New Contributor
New ContributorPCIe hard IP BAR to On-chip memory addressing
using Cyclone IV hard ip and On-chip memory 32B mapped to 0x-0x1F
BAR0 mapped to 0xA1200000-0xA0001F
Reading BAR0 at offset 0 should have access first byte of On-chip memory? Reading 0xff instea...
Hi,
May I know if you enable the PCIe BAR0? Have you try to performed SignalTap?
JohnT_Altera
Regular Contributor
Regular ContributorHi,
May I know if the issue is resolved after you unblock the BAR0?
- Markgel
Yes, it does - can access to the BARs memory.
