Forum Discussion
Markgel
New Contributor
New ContributorPCIe hard IP BAR to On-chip memory addressing
using Cyclone IV hard ip and On-chip memory 32B mapped to 0x-0x1F
BAR0 mapped to 0xA1200000-0xA0001F
Reading BAR0 at offset 0 should have access first byte of On-chip memory? Reading 0xff instea...
Hi,
May I know if you enable the PCIe BAR0? Have you try to performed SignalTap?
JohnT_Altera
Regular Contributor
Regular ContributorHi,
Could you share with me your Quartus design? How do you confirm that you are reading the correct addressing? Have you try to use SignalTap to tap the on chip memory IP interface?
MarkgelNew Contributor
New ContributorAttached the design. Regarding the addressing - trying to read and write to BAR0, but can't catch any activity for On chip memory signals using the SignalTap.
