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Markgel's avatar
Markgel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

PCIe hard IP BAR to On-chip memory addressing

using Cyclone IV hard ip and On-chip memory 32B mapped to 0x-0x1F BAR0 mapped to 0xA1200000-0xA0001F Reading BAR0 at offset 0 should have access first byte of On-chip memory? Reading 0xff instea...
  • JohnT_Altera's avatar
    JohnT_Altera
    5 years ago

    Hi,


    May I know if you enable the PCIe BAR0? Have you try to performed SignalTap?


JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Could you share with me your Quartus design? How do you confirm that you are reading the correct addressing? Have you try to use SignalTap to tap the on chip memory IP interface?


  • Markgel's avatar
    Markgel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Attached the design. Regarding the addressing - trying to read and write to BAR0, but can't catch any activity for On chip memory signals using the SignalTap.