PCIE example designs with external PHY without source synchronous transmit clock

I went through the MegaWizard for PCIE targeting the external PHYs, TI XIO1100 and NXP PX1011A. However, each of these have source synchronous transmit clock. I'm trying to find a sample external PHY design which doesn't have the transmit clock so that I can review the timing constraints. I'd like to see how the Gen2 250 MHz pipe clock and TX data is handled by the design (probably a PLL with phase shift) and specifically what the timing constraints look like for the TX signals. Are there such designs within the MegaWizard or elsewhere in Altera?