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SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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PCIe EP BAR0 size mismatch between Configuration value and FPGA value

Hi, I have Generated "Intel L-/H-Tile Avalon memory mapped for PCI Express" IP in PIO with BAR0 size set to 36 bits (64 G Bytes) On FPGA HW Platform, The EP BAR0 size appears to be 8 bits only,....
  • SivaKona's avatar
    SivaKona
    4 years ago

    Hi,

    By default the bar0_address_widths are set to 7.

    In standalone IP generation steps, The IP instance parameter value is not changing as per selected BAR0 Size.

    But when PCIe EndPpoint is generated as part of complete System design along with other components, a component instance Warning showed up sighting the mismatch in instance address width value and component address width value .

    Sync-ing both these address widths as per design Arch, fixed the issue.

    How can we control instance parameter while generating Standalone IP (Intel L/H Tile Avalon Memory Mapped for PCI Express)?

    Regards

    Siva Kona

SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi,

By default the bar0_address_widths are set to 7.

In standalone IP generation steps, The IP instance parameter value is not changing as per selected BAR0 Size.

But when PCIe EndPpoint is generated as part of complete System design along with other components, a component instance Warning showed up sighting the mismatch in instance address width value and component address width value .

Sync-ing both these address widths as per design Arch, fixed the issue.

How can we control instance parameter while generating Standalone IP (Intel L/H Tile Avalon Memory Mapped for PCI Express)?

Regards

Siva Kona