PCIe DMA transfer design code Compilation error.

Hi,

The expanded error massage you asked is attached (Quartus_Compilation_Error.png). Also, please see the underlined lines in the two fotos of verilog code where I have made a change (substitution.png and definition.png). Instead of initializing the "pcie_a10_hip_0_hip_pipe_sim_pipe_rate" to 1'b0 (please see the attached file DE5a_NET_Verilog_Error.png with error message, "Verilog HDL error at DE5A_NET.v(389): constant is not allowed"), I initialized it with a variable "entho" which is defined as wire[1:0]. With this hack, the project compiled without any error. Not sure that is what I am suppose to do to as a permanent solution. Do you have any suggestion regarding this?