Honored ContributorSo I've seen the Stratix V A7 board is PCI-Express gen 3 capable but the transfers, even with DMA are REAAAAALLY slow !
During aocl diagnose, the transfers are done using PCIe gen 2, so is there a way to "activate" PCIe gen 3 ?
Honored ContributorOn the FPGA side the PCIe host bandwidth will be limited by the Board Support Package IP. The Altera OpenCL SDK flow requires the board vendors' BSPs to handle CvP which does not support PCIe 3.0 (See https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug_aocl_s5_net_platform.pdf#page=17).
The BSP is not the only element influencing the PCIe host bandwidth. I would recommend double checking your PCIe slot is at least PCIe 2.0 x8 capable (some PCIe slots do not connect all lanes to the processor - e.g. a x8 physical slot might only connect x4 lanes electrically), your motherboard's/chipset's behavior might depend on other PCIe devices being plugged in the system, processor type, etc.
