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m_kumar's avatar
m_kumar
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Path Violation in timing analyzer

Hi , Iam working max10 fpga , in timing analyzer i'm getting path violations can i get any help to solve this problem. Report Timing: Found 200 setup paths (200 violated). Worst case slack is -0....
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Without seeing your design and a .sdc file, there's really no way to help with this. More details needed.