Forum Discussion
m_kumar
Occasional Contributor
Occasional ContributorPath Violation in timing analyzer
Hi ,
Iam working max10 fpga , in timing analyzer i'm getting path violations can i get any help to solve this problem.
Report Timing: Found 200 setup paths (200 violated). Worst case slack is -0....
sstrell
Super Contributor
Super ContributorWithout seeing your design and a .sdc file, there's really no way to help with this. More details needed.
