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Altera_Forum's avatar
Altera_Forum
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16 years ago

Output to Input Delays

How would I set up a SDC constraint to do the following:

I have a max combinational delay from output A to input C of 6ns

I have a max combinational delay from output B to input C of 10ns

Neither output signal is a clock, but they are both decoded register outputs (i.e. it's a synchronous design).

What is the proper command(s) to establish this constraint?

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    checkout help on "set_max_delay" in the TimeQuest Timing analyzer. From their man page:

    # Apply a 2ns max delay for an input port to an output port (TPD)

    set_max_delay -from [get_ports in

    [*]] -to [get_ports out

    [*]] 2.000

    -Dinesh
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    checkout help on "set_max_delay" in the TimeQuest Timing analyzer. From their man page:

    # Apply a 2ns max delay for an input port to an output port (TPD)

    set_max_delay -from [get_ports in

    [*]] -to [get_ports out

    [*]] 2.000

    -Dinesh

    --- Quote End ---

    Thanks for replying. I have been trying that. I think the problem I have is that TimeQuest doesn't see any connection between my outputs and my inputs. The outputs go to an external circuit (external to the FPGA) and then return.

    I've set my max delay to 2x my clock period, which should definitely cause some timing violations, but I see no change in the analysis.