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Altera_Forum
Honored Contributor
Honored ContributorOutput Timing Constraints
Hello, I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to ope...
Altera_ForumHonored Contributor
Honored ContributorThanks sstrell,
It's getting clearer now. I thought that set_output_delay was sufficient to constrain the logic. So now I can use the set_max_delay with a value of 10 ns from the output of the flip flop to the end of the computational logic. Will adding the set_output_delay cause any interference with the set_max_delay? Is there a rule of thumb for determining the values of input and output delay?
