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Altera_Forum's avatar
Altera_Forum
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8 years ago

Output Timing Constraints

Hello, I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to ope...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

But can't I just use the set_output_delay directly with the logic? I'm more concerned about ensuring that the combinational elements meets the required frequency of operation.