Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Output Timing Constraints

Hello, I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to ope...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Let me rephrase it. I have a design that has some combinational logic after registers stage and I'm asking about a way to constraint the timing of this logic cloud without adding an additional registers stage.