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Altera_Forum
Honored Contributor
Honored ContributorOutput Timing Constraints
Hello, I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to ope...
Altera_ForumHonored Contributor
Honored ContributorAre you saying that you are generating an output clock from the device? If so, you need a generated clock constraint targeted to the clock output port and a false path exception for the output clock.
What is this "mux at the output" you are referring to?
