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Altera_Forum
Honored Contributor
Honored ContributorOutput Timing Constraints
Hello, I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to ope...
Altera_ForumHonored Contributor
Honored ContributorJust constrain the clock to 100 MHz
create_clock -period 10 -name clk100Mhz [get_ports clk] See help: http://quartushelp.altera.com/14.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_clock.htm
