output doesn't toggle when simulating with other entities in Modelsim

Its actually a Verilog syntax problem.

The end of your "sending your read data" always block, you have this code:

end else
  state <= 8'h07;                    // signal
  sda_o_e <= 1'b0;                 // other_signal
end

Note there is no begin..end around the assignments. That means that only the state asignment is in the else, and the sda_o_e <= 1'b0; is in the original start-stop if block. This will mean this assignment to 0 always overrides whatever else was assigned.

its a bit of a gotcha in verilog that you're allowed to code without begin..end, but you must remember that only 1 line of code gets included.

Putting begin..end around it fixed the problem.