Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Orthodox way for testbench in modelsim

Hi, According to Verilog spec, initial begin# 20 clk=1; # 40 clk=0; # 60 clk=1; # 80 clk=0; End is legal, and can be compiled under modelsim. However, if we “ru...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

An "orthodox" way to create a testbench is to not use force at all. Force overrides what is already on a signal, and really only meant for fault injection.

As for running the testbench, the run command runs for the time specified in the command, so run 200 should run the testbench for 200 ns.# 20 delays a signal for 20*timeprecision. What have you got timeprecision set to? if it is 10 ns, then that will mean# 20 = 200 ns.

Try running the simulation for longer.