Occasional Contributor
Occasional ContributorI see the II increase, it jumps to 7 by inserting a fence exactly like you described (it jumps to 20 if the status variable is stored in memory). This is why the diagram was red in the picture attached above.
Also, if I compile with attibute memory, I obtain a different diagram wrt to yours (I don't have 4 stores, just one).
Still, I don't understand the argument about why channels are considered to be independent:
If Z==V, the compiler must enforce that the two operations are not swapped.
If this is not the case, please explain it clearly into your documentation.
New ContributorHere's one way to think of it
temp = Z; (cycle 5 above)
if(temp) write channel take in input temp;
read channel writes into Z
As long as temp=Z happens before read channel writes into Z, it doesn't matter what order the write channel and read channel happen.
