Forum Discussion
Occasional ContributorOrdering of channel operations
Occasional ContributorI see the II increase, it jumps to 7 by inserting a fence exactly like you described (it jumps to 20 if the status variable is stored in memory). This is why the diagram was red in the picture attached above.
Also, if I compile with attibute memory, I obtain a different diagram wrt to yours (I don't have 4 stores, just one).
Still, I don't understand the argument about why channels are considered to be independent:
- write channel take in input a variable V;
- read channel writes into a variable Z
If Z==V, the compiler must enforce that the two operations are not swapped.
If this is not the case, please explain it clearly into your documentation.
Douglas_P_IntelNew Contributor
Here's one way to think of it
temp = Z; (cycle 5 above)
if(temp) write channel take in input temp;
read channel writes into Z
As long as temp=Z happens before read channel writes into Z, it doesn't matter what order the write channel and read channel happen.
- Douglas_P_Intel
If I copy and paste the code above and add the mem fence I still see an II of ~1.
- Douglas_P_Intel
- tde_m
Hello,
Your reply with the tmp example clarified what is happening (thanks).
Still, I'm not understanding why is this happening: are there any explanations about the compiler not taking care of that dependencies?
Furthermore, having a cyclic dependencies (that the barrier does not resolve) is a thing that could happen frequently and ordering is what you rely on to build client-server patterns for example.
Concerning the higher II, I have the same II (7) even with the 19.1 compiler. I've attached the reports (the same occurs if I use the s10gx BSP included in the reports). Do you have any idea about why is this happening?
Thanks for you help
HRZFrequent Contributor
You are compiling against Stratix 10 while @douglas.prinn is probably compiling against Arria 10. On Arria 10, II is one after adding the mem_fence while on Stratix 10 it becomes 7. This is likely because the default target operating frequency on Arria 10 is 240 MHz, while on Stratix 10 it has been increased to 480 MHz. The solution is to probably not use channels at all (or multi-kernel designs, or the autorun kernel feature, or any other useful feature of the compiler that worked perfectly fine on previous generation FPGAs but for some unexplained reason, has "high overhead" on Stratix 10) as written in Section 9 of the Best Practices Guide. You can also try reducing the Fmax targert using the --fmax switch to reduce the II, but that will likely also lower your final post-place-and-route operating frequency.
