Hello, I'm currently struggling with enforcing the order of write/read to channels. I know, from the Intel programming guide, that two independent channels operation can be re-ordered by the compil...
@tde m @HRZ - Yes, you should assume all channel operations are independent even if you think there is a dependency. I know it looks like a read / write dependency on status, but the order that the channel operations are done is not dependent on the read / write order of status. The compiler will order the reads and writes to "status" correctly, but it considers the channel operations totally independent. It would be the same if you were reading or writing to 2 totally different regions in memory. You don't see the reads and writes to status because it's a register. If you force it to a RAM as shown below, it becomes clear. (See diagram)
computation_t __attribute__((memory) status;
cycle
4 - start read from CH1
5 - read (LD) from status (gets old data)
5 - write (ST) to status (result from CH1 read)
12 - start write to CH0 using old data from status