Optimisation issues

Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' on the final output. If I look at the RTL netlist, they're there, but in the finished output, they've gone (they don't work in the programmed FPGA, and SignalTap doesn't know about them), so obviously the optimiser has decided they're not used.

So, is there anywhere I can look to see why? Eg, outputs not used, inputs not connected, state not possible or something like that? What I'm doing at the moment is just changing, adding & removing bits in the hope that I can get some clues, but it seems like there must be a better way :-)

(I can't really post the source here because it's a little part of a complex project, so will be complex to extract in a way that doesn't possibly "fix" the problem in that sample).