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The only case of kernel deadlocks I have encountered were caused by channel ordering in multi-kernel designs. You seem to be mixing HDL and OpenCL; I guess there are a lot more stuff that could go wrong in that case. If the whole reason for mixing HDL with OpenCL for you is to avoid the extra buffer copy, you can already do that in pure OpenCL.
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Thank you for the reply.
The design has a pipeline implemented in HDL to collect data through a custom interface in the FPGA fabric. The goal was to reuse the existing, custom interface for collecting data and leverage OpenCL to post-process the captured data as a separate data path. Curiously, the data in RAM is entirely processed but the ARM application deadlocks waiting for the kernel's finish event.
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