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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

OpenCL error on code compilation

Dear all, I would like to use OpenCL SDK for a Terasic DE5-Net to deploy my algorithm (I am using Quartus 18.1 and OpenCL SDK 18.1). I successfully run the examples provided by Intel FPGA for OpenCL...
FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Thank you again for your support.

I do not have many loops with an high initiation interval but some variables that require a lot of resources are inside an high II. Thus, I am trying to reduce the II of loops and the ALUs and FFs utilization. No problem for me to post the code and I really appreciate your help. I also attached the report which can give you more details.

Moreover, I was able to reach only 50% of RAM but the ALUs and FFs were always well beyond the 100%. Could you please provide me some suggestions on how to reduce ALUs, FFs and also RAM? If possible, I would like to achieve the maximum performance in terms of execution time.

Federico