Forum Discussion
FCive
Occasional Contributor
7 years agoOpenCL error on code compilation
Dear all, I would like to use OpenCL SDK for a Terasic DE5-Net to deploy my algorithm (I am using Quartus 18.1 and OpenCL SDK 18.1). I successfully run the examples provided by Intel FPGA for OpenCL...
HRZ
Frequent Contributor
7 years agoIt is difficult to determine the reason for the high resource usage without seeing the source code; however, one thing I can say based on the snippet of the report you have posted is that due to the high initiation interval of your loop, all buffers inside of the loop need to be enlarged to accommodate for the high initiation interval, resulting in even higher resource usage. One thing you should consider doing is to optimize your loop and reduce the initiation interval. If you are comfortable with posting your kernel code, or a simplified version of it that exhibits the same issue, I might be able to give you a more concrete answer.