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Altera_Forum
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8 years ago

OpenCL Clock Speed and other stuff

Hi everyone. I am writing a code in OpenCL for a Stratix V FPGA and the return value for the CL_DEVICE_MAX_CLOCK_FREQUENCY is 1Ghz. Is there any way to increase the clock speed? Also is this...
Altera_Forum's avatar
Altera_Forum
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8 years ago

To complete sstrell's answer, the operating frequency is reported in the report named "acl_quartus_report.txt" after full placement and routing.