Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

OpenCL Clock Speed and other stuff

Hi everyone. I am writing a code in OpenCL for a Stratix V FPGA and the return value for the CL_DEVICE_MAX_CLOCK_FREQUENCY is 1Ghz. Is there any way to increase the clock speed? Also is this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Clock speed is set in the BSP. The clock speed your design will run at is in the reports generated by aoc. If for some reason your kernel can't run at the speed set by the BSP, aoc will compile it to run slower. This info would be included in the aoc-generated reports.