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Altera_Forum
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9 years ago

OpenCL Clock Speed and other stuff

Hi everyone. I am writing a code in OpenCL for a Stratix V FPGA and the return value for the CL_DEVICE_MAX_CLOCK_FREQUENCY is 1Ghz. Is there any way to increase the clock speed? Also is this...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That value shows nothing; the actual operating frequency will be determined after placement and routing of the kernel and is generally in the range of 150-300 MHz.