OpenCL 15.1 vs 17.1 with DE1-SoC (Cyclone V SoC)

Did you place and route the design using Quartus v17.1, or are you judging that it is not going to fit based on the area estimation report? The area estimation in v17.0 and v17.1 seems to have gotten more inaccurate compared to the previous versions, and designs that are predicted to overutilize FPGA resources might actually fit.

If, however, you are place and routing the design and it doesn't fit, then this could be part of the regressions introduced in v17.0; Altera made significant changes in the OpenCL compiler in v17.0, which seem to decrease performance and increase area usage in some cases. If this is indeed what is happening in your case, I recommend trying v16.1.2. In my experience, that is the most efficient version of the compiler in terms of performance and area usage. Furthermore, I recommend you report your issue to Altera so that they know the new versions of the compiler are performing worse than the older ones.