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LucaGiambastiani's avatar
LucaGiambastiani
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5 years ago

On-chip memory on Stratix 10

Hello, We are porting a project from Arria V (Quartus 16.1) to Stratix 10. The original one used the on-chip RAM memory IP with dual clock and Avalon-MM interfaces. It appears that this type of IP ...
  • LucaGiambastiani's avatar
    LucaGiambastiani
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    5 years ago

    Hello Syafieq,

    Thanks for the reply.

    We think that there are two problems with the TDP emulator. First, we need a memory with Avalon-MM interfaces, while the dual port RAM seems to have only conduit interfaces. Second, the page you linked says that the latencies are not guaranteed with a clock ratio less than 7. In our case the frequencies are 220 MHz and 250 MHz, so a ratio way below 7.

    Is it possible to configure this IP component in a way that is compatible with an Avalon-MM interface?

    Thanks,

    Luca