Honored Contributor
Honored ContributorI've just been playing with Qsys to see if it supports per-master address maps, and it appears it does, its just not that obvious how to use it.
Open up your Qsys design, and select the 'Address Map' tab. There should be a column per Avalon-MM master. Eg., one for your BAR0 control register PCIe slave (Qsys system master), and another for BAR1 or whatever you have in your system. You could also add a JTAG-to-Avalon-MM master or a Avalon-MM BFM master and connect them to some slaves to see that new columns are created. In the column for BAR0, your registers at address offset 0x28000 should be listed. Assuming that this is the only slave that decodes in that region, edit the address and set it to zero. This eliminates the MSBs from the BAR0 decode region. Rebuild the system. Look under fitter->resource section->pci express hard ip blocks. It'll tell you what the new BAR0 size is (it should be smaller). Download the new design to the FPGA, and lspci should show the smaller BAR0. Does the decoding logic work now? It should have worked in the previous setup, so I'm just trying to give you an alternative (but better, since the BAR is smaller) implementation. Cheers, Dave PS. For details on per-master address maps in Qsys, see Introduction to Qsys (OQSYS1000) http://www.altera.com/education/training/courses/oqsys1000 (specifically slides 44 and 45).
