On-Chip Memory in Qsys/Quartus

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Here is more context from the project itself:

The PCI BAR is set to Avalon Base 0x00000000 with a size of 19.

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19-bits is 512kB. lspci should show you this size. Note that this BAR size is way bigger than you need to display a few registers. Qsys is not very smart, in that it is using the absolute address map, not realizing that the MSBs are static, and hence the decode region can be reduced. If you move your registers to address zero, the BAR size will decrease.

edit: qsys's defaults are not very smart. you can create a master-specific address map the reduces the bar0 decode size. see the discussion further on in this thread.

Does the size of the BAR matter? Yes. If its too large, then the BIOS cannot allocate an address mapping to it. For example, with the PCIe examples in the users guide, they have a 256MB region for BAR0. I found my EliteBook would not boot with such a large BAR defined.

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The Address translation is a fixed table, 1 address page and the size of the address page is 20 bits --> Does this conflct with the above? I inherited this project and still coming up to speed on it.

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This is for outgoing PCIe transactions, i.e., transactions your Avalon-MM masters make to access the PCIe bus. Its basically the opposite direction to PCIe masters accessing your Avalon-MM system via BAR0.

Cheers,

Dave