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Altera_Forum
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14 years ago

On-Chip Memory in Qsys/Quartus

I have a design based on an Arria II GX part in which Qsys is utilized to generate a system made up of many different interfaces, other components and IP in the design. This system implements a PCIe...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Here is more context from the project itself:

The PCI BAR is set to Avalon Base 0x00000000 with a size of 19.

Maximum payload size: 256 Bytes

Peripheral Mode set to Requester/Completer with CRA selected

The Address translation is a fixed table, 1 address page and the size of the address page is 20 bits --> Does this conflct with the above? I inherited this project and still coming up to speed on it.

The Address Translation table contents for Page 0 is 0x0000000 and 0x0000000. I have passed the Linux question to the software team.

In the Qsys system contents and connections, the PCIe has the MM Master set to IRQ range 0-15 and the Slave set to range 0x00000000 to 0x3FFF