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The BAR is by itself, if I understand the question properly. There are other registers that access the other modules. Those all work fine. This one is a point in the contiguous memory map that has been identified. For example, this register sits at 0x28000 and another module consumes 0x27000 - 0x27FFF in memory space.
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There can be multiple address maps when dealing with PCIe devices.
If you had an Avalon-MM master component in your Qsys system, then it would have an address map containing all the devices (Avalon-MM slaves) it connects to.
Every PCIe BAR master also has an address map. Each BAR address map contains only the devices (Avalon-MM slaves) it connects to.
If you only map a single Avalon-MM slave with a few registers into say BAR0, then Qsys should only create a BAR0 window big enough to see the registers, i.e., Linux lspci should show a BAR0 size of maybe 256-bytes, or perhaps 4kB, depending on how smart Qsys is.
What does lspci indicate for the PCIe BAR you are using? Post the output of lspci -s <slot tuple> -vvv run as root.
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I assume that the OS, drivers, and the PCIe handles the BAR offsetting automatically. I did not write the OS drivers (Linux), but can forward questions to the team.
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No, it will not. If you use Linux to mmap the region, it has a granularity of 4kB (actually the granularity is PAGE_SIZE). If the BAR is only 256-bytes, then the BAR can show up within the 4kB region, but not necessarily at offset 0.
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With respect to the Avalon bridge diagnostic work you are speaking of, I am familiar with FPGA's and Altera devices from several years ago. I have not familiarized myself with the JTAG and Avalon-MM Bridge. I can give it a go and see what I find.
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Here's a tutorial I wrote:
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial Cheers,
Dave
Honored Contributor
